(1) Field of the Invention
This invention relates to semiconductor devices, and in particular, to CMP (Chemical Mechanical Polishing) of semiconductor substrates.
(2) Description of Related Art
In the fabrication of integrated circuits, semiconductor substrate surface planarity is of extreme importance. CMP (Chemical Mechanical Polishing) has been developed to produce smooth topographies on surfaces deposited on semiconductor substrates. Rough topography results when metal conductor lines are formed over a surface containing device circuitry. The metal conductor lines serve to interconnect discrete devices to form integrated circuits. The metal conductor lines are further insulated from the next interconnection level by thin layers of insulating material and holes formed through the insulating layers provide electrical access between successive conductive interconnection layers. In such wiring processes, it is necessary that the insulating layers have a smooth topography, because it is difficult to lithographically image and pattern layers applied to rough surfaces.
Briefly, the CMP processes involve holding and rotating a thin, flat semiconductor substrate against a wetted polishing surface under controlled chemical, pressure and temperature conditions. A chemical slurry containing a polishing agent, such as alumina or silica, is used as the abrasive material. Additionally, the chemical slurry contains selected chemicals which etch various surfaces of the substrate during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface.
Further, as integrated circuit device dimensions and device spacings decrease to less than 1 micron, device performance is severely impacted by the electrical properties of the insulating material used to separate the devices. For conductor line spacings less than 1 micron the RC (Resistance.times.Capacitance) circuit signal delay time increases rapidly. And for conductor line spacings less than 0.5 micron the RC delay becomes a critical limiting factor for the performance of the integrated circuit. Methods to alleviate the RC delay problem include using conductive materials having lower intrinsic resistivity and using insulating materials which have lower dielectric constants. As new conductive and insulating materials and new combinations of conductive and insulating materials are developed the requisite processes for fabricating the integrated circuits are challenged.
One of the most effective ways to alleviate the RC delay problem is to use low dielectric constant Spin-On-Glass (low-k SOG) materials for the interlevel insulating material. Siloxane based SOG is a class of low-k dielectric materials which has excellent gap-filling capability and reliability compatibility with semiconductor integrated circuits. The dielectric constant for SOG derived from methyl-siloxane is 3.8, compared to a dielectric constant between 6 and 8 for deposited silicates. And, the dielectric constant for SOG derived from methyl-silsesquloxane is 2.7. However, state-of-the-art CMP processes utilizing conventional KOH based CMP slurries using alumina or silica as the abrasive material are not effective for polishing the low-k siloxane based SOG materials. For example, when using a conventional KOH based CMP slurry containing silica abrasive particles the polish removal rate for siloxane based SOG materials is between about 130 and 250 Angstroms/min., compared to about 1150 Angstroms/min. for the polish removal rate of silicate layers deposited by plasma processes. Therefore, there is an ongoing challenge to develop new CMP processes and new CMP polishing slurries to effectively and efficiently polish low-k siloxane based SOG materials.
While numerous improved CMP methods have been developed, as shown in the following U.S. Patents, these methods are not suitable for polishing low-k siloxane based SOG materials at a high removal rate. U.S. Pat. No. 5,733,819 entitled "Polishing Composition" granted Mar. 31, 1998 to Hitoshi Kodama et al describes a CMP slurry for polishing silicon dioxide. The slurry comprises silicon nitride fine powder, water and an acid and further additions of titania, zirconia, alumina or silica.
U.S. Pat. No. 5,704,987 entitled "Process For Removing Residue From A Semiconductor Wafer After Chemical-Mechanical Polishing" granted Jan. 6, 1998 to Cuc Kim Huynh et al describes a method for cleaning the surface of a semiconductor wafer after CMP. Residual slurry particles adhered to the wafer surface are removed by changing the oxide surface to hydrophilic, using TMAH (Tetra-Methyl-Ammonium Hydroxide) as a surfactant.
U.S. Pat. No. 5,468,326 entitled "Apparatus For Polishing A Diamond Or Carbon Nitride Film By Reaction With Oxygen Transported To The Film Through A Superionic Conductor In Contact With The Film" granted Nov. 21, 1995 to Jerome J. Cuomo et al describes a static method of polishing a diamond or carbon nitride film, in which a yttria-stabilized zirconia layer or, alternately, a zirconia layer is placed in contact with the diamond or carbon nitride film in the presence of oxygen.
U.S. Pat. No. 5,525,191 entitled "Process For Polishing A Semiconductor Substrate" granted Jun. 11, 1996 to Papu D. Maniar et al describes a zirconium dioxide based polishing slurry in which the pH of the slurry is adjusted by changing or adding potassium hydroxide or ammonium hydroxide to the slurry.
U.S. Pat. No. 5,480.476 entitled "Activated Polishing Compositions" granted Jan. 2, 1996 to Lee M. Cook et al shows activated polishing slurries, which contain silica, zirconia, water and ammonium hydroxide, and are prepared by a co-milling process.
U.S. Pat. No. 5,154,023 entitled "Polishing Process For Refractory Materials" granted Oct. 13, 1992 to Piran Sioshansi teaches a process for polishing materials such as diamond, sapphire, ruby and Si.sub.3 N.sub.4, in which the surface is pre-softened by ion implantation, followed by mechanical polishing with an abrasive compound containing natural diamond, corundum, SiC, Al.sub.2 O.sub.3, ZrO, MgO, Cr.sub.2 O.sub.3, or Fe.sub.2 O.sub.3.
The present invention is directed to a novel method of CMP of low-k siloxane based SOG materials using a CMP slurry containing ZrO.sub.2 as the polishing abrasive and a surfactant such as TMAH (Tetra-Methyl-Ammonium Hydroxide) or TBAH (Tetra-Butyl-Ammonium Hydroxide). The slurry composition and method of the present invention permits planarization of low-k siloxane based SOG materials at a high enough removal rate to make the CMP process efficient and practical for use in the fabrication of multilevel semiconductor integrated circuits. The CMP slurry composition and method of the present invention improves the polish removal rate of low-k siloxane based SOG materials to 4000 Angstroms/min., compared to a polish removal rate of 170 Angstroms/min. when using a conventional KOH based CMP slurry containing silica particles. The CMP slurry composition and method of the present invention, also, achieves a CMP selectivity ratio as high as 8, where the CMP selectivity ratio is the ratio of the polish removal rate of low-k siloxane based SOG to the polish removal rate of deposited silicon oxide. Achievement of this high CMP selectivity ratio permits deposited silicon oxide to act as a polish stop layer in the CMP process for planarizing low-k siloxane based SOG insulators.